Search Results - "Reversible computing"

Optimized Fredkin Gate and its Application to Design an Ancilla-Delay-Cost Efficient (2i∗j) Reversible RAM.

Authors: Chowdhury, Barnali Awasthi, Shashank Metya, Sanjeev Kumar

Source: Circuits, Systems & Signal Processing. Jan2026, Vol. 45 Issue 1, p364-392. 29p.

Subjects: Reversible computing, Random access memory, Quantum gates, Quantum computing, Nanotechnology, Computational complexity

Robust and compact reversible logic gate for low-power and high-performance computing.

Authors: Rajput, Anju Kumawat, Renu Srinivasulu, Avireni et al.

Source: Scientific Reports. 1/1/2026, Vol. 16 Issue 1, p1-15. 15p.

A Modified Technique for the Detection and Exact Localization of Missing Gate Faults in Reversible Circuits.

Authors: Mondal, Bappaditya Datta, Subrata Sarkar, Sutapa

Source: IETE Journal of Research; Oct2025, Vol. 71 Issue 10, p3383-3399, 17p

Logical Fault Detection Approach for Mixed Control Flipping Faults in Reversible Circuits.

Authors: Handique, Mousum Prasad, Amrit

Source: IETE Journal of Research. Sep2025, Vol. 71 Issue 9, p3139-3155. 17p.

Subjects: Reversible computing, Fault diagnosis, Digital electronics, Quantum computing

Deep Collocation Method: A Numerical Algorithm Combining Reversible Neural Network and Spectral Differentiation for Solving the Incompressible Navier–Stokes Equations.

Authors: Chen, Ruilin Ma, Guihui Fang, Ming

Source: International Journal for Numerical Methods in Engineering. 4/15/2026, Vol. 127 Issue 7, p1-24. 24p.

Subjects: Reversible computing, Numerical differentiation, Discretization methods, Computational fluid dynamics, Artificial neural networks, Iterative methods (Mathematics), Incompressible flow

DESIGN OF REVERSIBLE FULL ADDER OR SUBTRACTOR BASED ON EPOE EXPRESSIONS FOR COMPUTATIONAL APPLICATIONS.

Authors: RAMA KRISHNA REDDY, E. AASHRUTHA SAI PUSHPA, F. P. BALA NAGESWARI, G. G. et al.

Source: i-Manager's Journal on Electronics Engineering; Sep2025, Vol. 15 Issue 4, p10-20, 11p

Industry perspective: Limits of energy efficiency for conventional CMOS and the need for adiabatic reversible computing.

Authors: Frank, Michael P. Edwards, Alexander J.

Source: APL Electronic Devices. Sep2025, Vol. 1 Issue 3, p1-6. 6p.

Novel Design of Resource‐Constrained Quantum Reversible Logic Gates at Optimal Cost and Depth.

Authors: Prajapati, Mamtha Killana, Kalyan Babu Curreli, Nicola

Source: Journal of Nanotechnology; 8/6/2025, Vol. 2025, p1-17, 17p

Design and Analysis of RMFAS CORDIC II Rotator for FPGA.

Authors: A, Anjana R, Nakkeeran Jothikumar R, Ramya

Source: IETE Journal of Research; Jul2025, Vol. 71 Issue 7, p2430-2440, 11p

Low-Power Ternary ALU with Reversible Gates and Gate Diffusion Multiplexers in the Carbon Nanotube Technology.

Authors: Murali Krishna, P. Vishnu Vardhan, D.

Source: IETE Journal of Research. Feb/Mar2026, Vol. 72 Issue 2/3, p586-595. 10p.

Subjects: Reversible computing, Power aware computing, Computer performance, Carbon nanotubes, Speed

An Optimized Reversible Multiplier with Sklansky Adder for Next-Generation ALUs.

Authors: Yadav, Rishu Kushwaha, Nagendra Mishra, Sandeep et al.

Source: IETE Journal of Research. Jan-Jun2026, Vol. 72 Issue 1, p271-283. 13p.

Subjects: Reversible computing, Computer arithmetic, Systems on a chip, Field programmable gate arrays, Power aware computing

Optimized Reversible Full Adder Using Lithium Niobate MZI Based Peres Gate.

Authors: Chowdhury, Barnali Awasthi, Shashank Metya, Sanjeev Kumar

Source: Circuits, Systems & Signal Processing. Jan2026, Vol. 45 Issue 1, p30-45. 16p.

Subjects: Reversible computing, Lithium niobate, Interferometers, Optical engineering, Quantum gates, Energy dissipation, Logic circuits, Quantum computers

Area-efficient low-power image watermarking architecture using faithful approximation and reversible logic.

Authors: D., Silambarasan K.N., Vijeyakumar K, Saranya

Source: Multimedia Tools & Applications; May2025, Vol. 84 Issue 18, p19749-19783, 35p

Startup working on 'reversible computing' chip for AI says initial tests show a 50% energy savings.

Authors: Kahn, Jeremy (AUTHOR)

Source: Fortune.com. 5/21/2025, pN.PAG-N.PAG. 1p.

Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA.

Authors: Tiwari, Kanchan S. Wahul, Revati M. Shinde, Sagar D. et al.

Source: Mathematical Modelling of Engineering Problems. Feb2025, Vol. 12 Issue 2, p730-744. 15p.

NONINTERFERENCE ANALYSIS OF REVERSIBLE SYSTEMS: AN APPROACH BASED ON BRANCHING BISIMILARITY.

Authors: ESPOSITO, ANDREA ALDINI, ALESSANDRO BERNARDO, MARCO et al.

Source: Logical Methods in Computer Science (LMCS); 2025, Vol. 21 Issue 1, p1-28, 28p

The group of reversible turing machines: subgroups, generators, and computability – CORRIGENDUM.

Source: Forum of Mathematics, Sigma. 2025, Vol. 13, p1-42. 42p.

PSPACE-Completeness of Reversible Deterministic Systems.

Authors: Demaine, Erik D. Hearn, Robert A. Hendrickson, Dylan et al.

Source: International Journal of Foundations of Computer Science. Nov2025, Vol. 36 Issue 7, p1041-1062. 22p.

Subjects: Reversible computing, Computational complexity, Deterministic algorithms, Planning techniques, Constraint programming

Energy‐Efficient and Area‐Optimized Reversible Carry Select Adder.

Authors: Murugesan, Praveena S., Palani V., Divya et al.

Source: IET Circuits, Devices & Systems (Wiley-Blackwell). 12/9/2025, Vol. 2025, p1-10. 10p.

Subjects: Reversible computing, Quantum computing, Digital technology, Energy consumption, Field programmable gate arrays, Very large scale circuit integration

A Universal Reversible Turing Machine that Directly Simulates Reversible Counter Machines.

Authors: Morita, Kenichi¹ km@hiroshima-u.ac.jp

Source: Computer Science Journal of Moldova. 2024, Vol. 32 Issue 3, p425-445. 21p.