Search Results - "Computer arithmetic"

Design of Logic Level Pruning Approximate Arithmetic Circuits Using TIGFET.

Authors: Naresh, Kattekola Padma Sai, Y. Ganesh, Ch. et al.

Source: Circuits, Systems & Signal Processing. Jan2026, Vol. 45 Issue 1, p647-663. 17p.

Subjects: Computer arithmetic, Field-effect transistors, Electric currents, Approximation algorithms, Electronic circuit design, Transistors

Bio-Inspired Constant-Time Arithmetic Kernels in Hybrid Membrane–Neural Spiking P Systems.

Authors: Vázquez, Eduardo Guillen, Josue J. Vázquez, Daniel-Eduardo et al.

Source: Mathematics (2227-7390). Mar2026, Vol. 14 Issue 5, p783. 23p.

Optimal IIR Filter Design and FPGA Realization.

Authors: Eddla, Arunjyothi Pappu, V. Y. Jayasree

Source: Engineering, Technology & Applied Science Research; Feb2026, Vol. 16 Issue 1, p31009-31014, 6p

Design of compressor-based multipliers using simulated annealing for arithmetic logic unit.

Authors: Pavitra, Y. J. Manikandan, J.

Source: Neural Computing & Applications. Nov2025, Vol. 37 Issue 33, p27747-27757. 11p.

Subjects: Simulated annealing, Computer arithmetic, Electronic circuit design, Mathematical optimization, Technical specifications, Field programmable gate arrays

Design and Performance Analysis of an 8-3 Approximate Compressor-Based Multiplier for Image Blending Application.

Authors: Gupta, Sanjiv Kumar Dhawan, Amit Tiwari, Manish et al.

Source: IETE Journal of Research. Jul2025, Vol. 71 Issue 7, p2441-2452. 12p.

Subjects: Computer arithmetic, Image fusion, Approximation algorithms, Computer performance

Design and Analysis of RMFAS CORDIC II Rotator for FPGA.

Authors: A, Anjana R, Nakkeeran Jothikumar R, Ramya

Source: IETE Journal of Research; Jul2025, Vol. 71 Issue 7, p2430-2440, 11p

An Optimized Reversible Multiplier with Sklansky Adder for Next-Generation ALUs.

Authors: Yadav, Rishu Kushwaha, Nagendra Mishra, Sandeep et al.

Source: IETE Journal of Research. Jan-Jun2026, Vol. 72 Issue 1, p271-283. 13p.

Subjects: Reversible computing, Computer arithmetic, Systems on a chip, Field programmable gate arrays, Power aware computing

Machine Learning Using Approximate Computing.

Authors: Balasubramanian, Padmanabhan Zaheen, Syed Mohammed Mosayeeb Al Hady Maskell, Douglas L.

Source: Journal of Low Power Electronics & Applications; Jun2025, Vol. 15 Issue 2, p21, 15p

Axis‐Normalized Ray‐Box Intersection.

Authors: Friederichs, F. Benthin, C. Grogorick, S. et al.

Source: Computer Graphics Forum; May2025, Vol. 44 Issue 2, p1-9, 9p

Design Space Exploration for Approximate Circuits Based on Arithmetic Calculus Modeling.

Authors: Aoun, Alain Masadeh, Mahmoud Hasan, Osman et al.

Source: Journal of Circuits, Systems & Computers. Apr2026, p1. 32p. 15 Illustrations.

Enlarged GKB and RSVD for KP approximations illustrated for mixed precision ℓ1 image restoration.

Authors: Alsubhi, Abdulmajeed Renaut, Rosemary A.

Source: Numerical Algorithms; Apr2026, Vol. 101 Issue 4, p2245-2267, 23p

On the accurate computation of the Newton form of the Lagrange interpolant.

Authors: Khiar, Y. Mainar, E. Royo-Amondarain, E. et al.

Source: Numerical Algorithms. Mar2025, Vol. 98 Issue 3, p1553-1573. 21p.

Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA.

Authors: Tiwari, Kanchan S. Wahul, Revati M. Shinde, Sagar D. et al.

Source: Mathematical Modelling of Engineering Problems. Feb2025, Vol. 12 Issue 2, p730-744. 15p.

CVD grown bilayer MoS2 based artificial optoelectronic synapses for arithmetic computing and image recognition applications.

Authors: Patra, Umakanta Sikdar, Subhrajit Padhan, Roshan et al.

Source: Journal of Physics D: Applied Physics; 2026, Vol. 59 Issue 11, p1-13, 13p

Resource-Efficient Model Predictive Control on a Low-End Field-Programmable Gate Array for DC Motor Speed Control.

Authors: Pratama, Aulia Rasyid Istiyanto, Jazi Eko Dharmawan, Andi

Source: International Journal of Robotics & Control Systems; 2026, Vol. 6 Issue 2, p1079-1099, 21p

RG-ALU: A REVERSIBLE LOGIC GATE-BASED ARITHMETIC LOGIC UNIT IN AN FPGA.

Authors: Ramakrishnan, Kannan K., Vidhya

Source: Proceedings on Engineering Sciences; 2026, Vol. 8 Issue 1, p305-310, 6p

Optimised ALU Design in Quantum Cell Automata Platform with Energy Analysis.

Authors: Jana, Sachindeb Chakrabarti, Kisalaya Sarkar, Angsuman

Source: Journal of Integrated Circuits & Systems; 2026, Vol. 21 Issue 1, p1-10, 10p

Junctionless MOSFET-based Adiabatic Adder for Energy-Efficient Application.

Authors: Ganguli, Tanushree De, Foyjun Ghosh, Sudipta et al.

Source: Journal of Integrated Circuits & Systems; 2026, Vol. 21 Issue 1, p1-7, 7p

Measuring 3- and 4-Moduli Sets Delay Per Bit in Residue Number System: A Survey.

Authors: Torabi, Z. Barzegaran, V.

Source: IETE Journal of Research. Apr2024, Vol. 70 Issue 4, p3795-3803. 9p.

Subjects: Computer arithmetic, Literature

A hybrid forward/reverse converter in reversible logic to reduce hardware complexity of residual number system.

Authors: Asadpour, Ailin Sabbagh, Amir Emrani, Azadeh

Source: Majlesi Journal of Electrical Engineering. Jun2024, Vol. 18 Issue 2, p1-15. 15p.

Subjects: Computer arithmetic, Computer circuits, Reversible computing, Technological innovations, Number systems