Search Results - "Digital electronics"

Implementation of Energy and EDP Efficient Adder Circuits at Sub Threshold Regime for Signal Processing Applications.

Authors: PAMULETI, CHALLA DAULA, S. M. SHAMSHEER GUNDALA, SRINIVASULU et al.

Source: Journal of Active & Passive Electronic Devices; 2026, Vol. 20 Issue 2, p159-173, 15p

Study and Design of the RF Part of a Passive RFID Tag at 900MHz Frequency for the ISO 18000-6c Standards.

Authors: Habibi, Sanae Bendali, Abdelhak Habibi, Mohamed et al.

Source: International Journal of Microwave & Optical Technology; Mar2026, Vol. 21 Issue 2, p124-131, 8p

MODELLING OF SUBTHRESHOLD CURRENTS IN SB-CNTFETs.

Authors: MARANI, ROBERTO PERRI, ANNA GINA

Source: i-Manager's Journal on Electronics Engineering; Mar2026, Vol. 16 Issue 2, p1-6, 6p

Optimized Inexact adder for Approximate Computing Applications.

Authors: G., Narmadha S., Deivasigamani Pugazhendiran, P. et al.

Source: Journal of Engineering Sciences. Mar/Apr2026, Vol. 54 Issue 2, p74-80. 7p.

Optimal IIR Filter Design and FPGA Realization.

Authors: Eddla, Arunjyothi Pappu, V. Y. Jayasree

Source: Engineering, Technology & Applied Science Research; Feb2026, Vol. 16 Issue 1, p31009-31014, 6p

Power Efficient Memory based Transistor-Memristor with CMOS Configuration Hybrid Mode Circuits for Future Neuromorphic Computation.

Authors: T., Harish Gupta, Kiran A. G., Pavithra et al.

Source: Grenze International Journal of Engineering & Technology (GIJET); Jan2026, Vol. 12 Issue Part2, p4115-4121, 7p

A Novel Design of High-Performance CNTFET-Based Full Adder Using Optimized XORXNOR Cell.

Authors: SHARMA, UMA JHAMB, MANSI

Source: Journal of Active & Passive Electronic Devices; 2026, Vol. 20 Issue 1, p49-66, 18p

Study on Progress Towards Carbon Nanotube Adder Circuits Capable of Energy Efficient Computing in Integrated Systems.

Authors: DHOLVAN, MOHAN CHAKALI, CHANDRASEKHAR K., NAGENDRAKUMAR et al.

Source: Journal of Active & Passive Electronic Devices; 2026, Vol. 20 Issue 1, p13-25, 13p

Enhancing information security and fault coverage in BIST with non-linear register updation.

Authors: Chinnappa Gounder, Kalamani D, Mythrayee A, Kodieswari et al.

Source: Information Security Journal: A Global Perspective; 2026, Vol. 35 Issue 1, p237-250, 14p

Study and Implementations of Adder Circuits for Energy and EDP Efficient Computing Systems.

Authors: T., RAMASWAMY RAO, S. P. V. SUBBA BASHA, MOHAMMED MAHABOOB et al.

Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p255-269, 15p

The evolution of test and measurement instruments: The increasing use of digital electronics in military operations, and the rise of artificial intelligence CAD and machine learning are pushing test technology forward.

Authors: Whitney, Jamie

Source: Military & Aerospace Electronics. Nov/Dec2025, Vol. 36 Issue 6, p27-32. 6p.

Subjects: Artificial intelligence, Digital electronics, Digital twin, Digital computer simulation, Forecasting, Embedded computer systems, Measuring instruments

Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing.

Authors: CHANDRASEKHAR, CHAKALI DAS, SARI MOHAN JAYACHANDRANATH, S. et al.

Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p301-312, 12p

Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process.

Authors: PRASAD, T. JAYACHANDRA CHENNAKESAVULU, M. REDDY, BOJJ A. RAMESH et al.

Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p283-299, 17p

Design and Performance Analysis of Power-Efficient Multipliers for Image Sharpening.

Authors: Mendez, Tanya Badiger, Manjunatha

Source: Engineering, Technology & Applied Science Research; Dec2025, Vol. 15 Issue 6, p28460-28465, 6p

COMPARATIVE ANALYSIS OF DIGITAL CIRCUITS IN CNTFET AND CMOS TECHNOLOGY: A REVIEW.

Authors: MARANI, ROBERTO PERRI, ANNA GINA

Source: i-Manager's Journal on Electronics Engineering; Dec2025, Vol. 16 Issue 1, p1-8, 8p

Metal-organic framework impregnated sponge-based TENG as a binary input device for logic gate simulation and power plant control.

Authors: Palakkattiri Krishnan, Nitha Khandelwal, Gaurav Chandrasekhar, Arunkumar

Source: Discover Nano; 10/30/2025, Vol. 20 Issue 1, p1-16, 16p

VLSI Implementation of High‐Speed and Area‐Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications.

Authors: Perumal, Vivek Karthick Jayabalan, Ramesh Paul, Eldho et al.

Source: Journal of Electrical & Computer Engineering; 10/24/2025, Vol. 2025, p1-11, 11p

МЕХАНІЗМИ СХЕМОТЕХНІЧНОГО МОДЕЛЮВАННЯ НА ОСНОВІ ВЕКТОРНОЇ ЛОГІКИ.

Authors: В. І., Хаханов В. І., Обрізан О. Ю., Шевченко et al.

Source: Radio Electronics, Computer Science, Control; 2025, Issue 4, p219-232, 14p

An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications.

Authors: Dhanasekar, S. Govindaraj, V. Augustine Fletcher, A. S.

Source: International Journal of Electronics. May2026, Vol. 113 Issue 5, p937-957. 21p.

A Novel Approach: Hybrid Full Adder Design Tailored for Multistage Architecture.

Authors: Kumar, Dinesh Karuppanan, P.

Source: Circuits, Systems & Signal Processing. Apr2026, Vol. 45 Issue 4, p2633-2654. 22p.

Subjects: Digital electronics, Signal integrity (Electronics), Electronic equipment