Search Results - "Instruction set processors"

Lightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithms.

Authors: Akçay, Latif Yalçın, Berna Örs

Source: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Jan2025, Vol. 50 Issue 2, p835-849. 15p.

Subjects: Application-specific instruction-set processors, Mathematics software, Computer software, Information design, Cryptography

ArchiLaSimu : Un émulateur d'Architecture Von Neumann pour LaSimulation. (French)

Authors: Myara, Mikhaël Virazel, Arnaud

Source: J3eA (1638-5705); 2025, Vol. 24, p1-10, 10p

Research on SIMD Instruction Sequence Generation Method for Vector DSP Processor.

Authors: Hu, Yonghua Liu, Fangjun Zhang, Huifu et al.

Source: Concurrency & Computation: Practice & Experience; Jan2026, Vol. 38 Issue 1, p1-9, 9p

Speeding up the Discrete Cosine Transform Through Custom Operations and Fixed-Point Arithmetic.

Authors: Akçay, Latif Engin, Mustafa Alptekin

Source: Journal of Innovative Science & Engineering (JISE); 2025, Vol. 9 Issue 2, p268-278, 11p

High-Performance Computing in the Residue Number System.

Authors: Nikolaychuk, Y. Pitukh, I.

Source: Cybernetics & Systems Analysis; Jul2025, Vol. 61 Issue 4, p685-696, 12p

Broadcom Stock Rises On Meta AI Chip Partnership.

Authors: SEITZ, PATRICK (AUTHOR)

Source: Investors Business Daily. 4/15/2026, pN.PAG-N.PAG. 1p.

Subjects: Stock prices, Meta Platforms Inc., Facebook (Web resource), High technology industries, Application-specific instruction-set processors, Business partnerships

Uncovering hidden threats: A format-driven approach to dsp instruction set vulnerability discovery.

Authors: Luo, Yongzhen Huang, Zhongkai Duan, Wenhui et al.

Source: Computers & Security; Mar2026, Vol. 162, pN.PAG-N.PAG, 1p

An efficient RISC-V processor with customized instruction set for sparse DNN acceleration on embedded system.

Authors: Jiang, Bowen Ding, Jianyang Zhang, Huachen et al.

Source: Journal of Systems Architecture; Feb2026, Vol. 171, pN.PAG-N.PAG, 1p

Capstone Project: CPU Design with Multiplexer.

Authors: Di Mauro, Anthony F. Hawkins, Michael C. Lindsey, Bradley K. et al.

Source: Proceedings of the ASEE Annual Conference & Exposition. 2024, p1-7. 7p.

Compilation and Worst-Case Reaction Time Analysis for Multithreaded Esterel Processing.

Authors: Boldt, Marian Traulsen, Claus von Hanxleden, Reinhard

Source: EURASIP Journal on Embedded Systems. 1/7/2009, p1-21. 21p. 10 Diagrams, 3 Charts, 1 Graph.

Subjects: Application-specific instruction-set processors, Synchronous data transmission systems, Compilers (Computer programs), Digital communications, Language & education, Interlanguage (Language learning)

Empirical Evaluation of Some Features of Instruction Set Processor Architectures.

Authors: Bell, G. Siewiorek, D. Fuller, S. H. et al.

Source: Communications of the ACM. Mar1977, Vol. 20 Issue 3, p143-153. 11p. 18 Charts.

Subjects: Instruction set processors, Programming languages, Computers, Computer architecture, Computer input-output equipment, Computer systems

Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors.

Authors: KAMAL, MEHDI AFZALI-KUSHA, ALI SAFARI, SAEED et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Apr2014, Vol. 10 Issue 3, p19:1-19:25, 25p

Automatic generation of compiler backends.

Authors: Brandner, Florian Pavlu, Viktor Krall, Andreas

Source: Software: Practice & Experience; Feb2013, Vol. 43 Issue 2, p207-240, 34p

Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm.

Authors: Ahmed, O. Areibi, S. Grewal, G.

Source: International Journal of Reconfigurable Computing; 2013, p1-33, 33p

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine.

Authors: Hassan, Hanan M. Mohammed, Karim Shalash, Ahmed F.

Source: EURASIP Journal on Embedded Systems; Feb2012, Vol. 2012 Issue 1, p1-18, 18p

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.

Authors: Grad, Mariusz Plessl, Christian

Source: International Journal of Reconfigurable Computing; 2012, p1-21, 21p

Network Anomaly Detection Based on Wavelet Analysis.

Authors: Wei Lu Ghorbani, Ali A.

Source: EURASIP Journal on Advances in Signal Processing; 2009, Special section p1-16, 16p, 2 Diagrams, 14 Charts, 4 Graphs

Prefabrication and Postfabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.

Authors: Chattopadhyay, A. Ishebabi, H. Chen, X. et al.

Source: ACM Transactions on Embedded Computing Systems; Jul2008, Vol. 7 Issue 4, p40-40:31, 31p, 8 Diagrams, 13 Charts, 1 Graph

THE BEST OF MAXIMUM PC.

Source: Maximum PC; Feb2022, Issue 200, p50-55, 6p, 19 Color Photographs

Compact and low‐power ASIP design for lightweight PUF‐based authentication protocols.

Authors: Aysu, Aydin Gulcan, Ege Moriyama, Daisuke et al.

Source: IET Information Security (Wiley-Blackwell). Sep2016, Vol. 10 Issue 5, p232-241. 10p.

Subjects: Application-specific instruction-set processors, Application-specific integrated circuits, Instruction set processors, Logic design, Physical mobility