Search Results - "Pathania, Anuj"

Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation.

Authors: YIXIAN SHEN SCHREUDERS, LEO PATHANIA, ANUJ et al.

Source: ACM Transactions on Embedded Computing Systems; 2023 Suppl5s, Vol. 22, p1-26, 26p

BrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge Devices.

Authors: Hoffman, Alexander Pathania, Anuj Kindt, Philipp H. et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2020, Issue 57, p1310-1315, 6p

Temperature-aware compact SER modeling using model order reduction.

Authors: Stoikos, Pavlos Axelou, Olympia Tsoumanis, Pelopidas et al.

Source: Microprocessors & Microsystems; Jun2026, Vol. 122, pN.PAG-N.PAG, 1p

CASCADE: High Throughput Data Streaming via Decoupled Access-Execute CGRA.

Authors: WIJERATHNE, DHANANJAYA ZHAOYING LI KARUNARATHNE, MANUPA et al.

Source: ACM Transactions on Embedded Computing Systems; 2019Special Issue, Vol. 18 Issue 5s, p1-26, 26p

QoS-Aware Stochastic Power Management for Many-Cores.

Authors: Pathania, Anuj Khdr, Heba Shafique, Muhammad et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2018, Issue 55, p751-756, 6p

Distributed Scheduling for Many-Cores Using Cooperative Game Theory.

Authors: Pathania, Anuj Venkataramani, Vanchinathan Shafique, Muhammad et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2016, p785-790, 6p

Integrated CPU-GPU Power Management for 3D Mobile Games.

Authors: Pathania, Anuj Qing Jiao Prakash, Alok et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2014, p227-232, 6p

HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction.

Authors: Wijerathne, Dhananjaya Li, Zhaoying Pathania, Anuj et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Oct2022, Vol. 41 Issue 10, p3290-3303, 14p

ChordMap: Automated Mapping of Streaming Applications Onto CGRA.

Authors: Li, Zhaoying Wijerathne, Dhananjaya Chen, Xianzhang et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Feb2022, Vol. 41 Issue 2, p306-319, 14p

Power-Efficient Heterogeneous Many-Core Design With NCFET Technology.

Authors: Salamin, Sami Rapp, Martin Pathania, Anuj et al.

Source: IEEE Transactions on Computers; Sep2021, Vol. 70 Issue 9, p1484-1497, 14p

High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors.

Authors: Wang, Siqi Ananthanarayanan, Gayathri Zeng, Yifan et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Sep2020, Vol. 39 Issue 10, p2254-2267, 14p

Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores.

Authors: Rapp, Martin Sagi, Mark Pathania, Anuj et al.

Source: IEEE Transactions on Computers; Jan2020, Vol. 69 Issue 1, p1-13, 13p

PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications.

Authors: Maity, Arka Pathania, Anuj Mitra, Tulika

Source: Journal of Low Power Electronics & Applications; Dec2020, Vol. 10 Issue 4, p31, 1p

Energy Efficiency for Clustered Heterogeneous Multicores.

Authors: Pagani, Santiago Pathania, Anuj Shafique, Muhammad et al.

Source: IEEE Transactions on Parallel & Distributed Systems. May2017, Vol. 28 Issue 5, p1315-1330. 16p.

Subjects: Multicore processors, Computer systems, Heterogeneity, Computer architecture, Algorithms

Optimal Greedy Algorithm for Many-Core Scheduling.

Authors: Pathania, Anuj Venkatramani, Vanchinathan Shafique, Muhammad et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Jun2017, Vol. 36 Issue 6, p1054-1058. 5p.

Subjects: Greedy algorithms, Dynamic programming, Integrated circuits, Computer scheduling, Resource management

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.

Authors: Khdr, Heba Pagani, Santiago Sousa, Ericles et al.

Source: IEEE Transactions on Computers; Mar2017, Vol. 66 Issue 3, p488-501, 14p