Search Results - "Pomeranz, Irith"

On Functional Broadside Tests With Functional Propagation Conditions.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; June 2011, Vol. 19 Issue 6, p1094-1098, 5p

Broadside and Functional Broadside Tests for Partial-Scan Circuits.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; June 2011, Vol. 19 Issue 6, p1104-1108, 5p

Static Test Data Volume Reduction Using Complementation or Modulo-M Addition.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; June 2011, Vol. 19 Issue 6, p1108-1112, 5p

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; February 2011, Vol. 19 Issue 2, p333-337, 5p

Fixed-State Tests for Delay Faults in Scan Designs.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; January 2011, Vol. 19 Issue 1, p142-146, 5p

On Undetectable Faults and Fault Diagnosis.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; November 2010, Vol. 29 Issue 11, p1832-1837, 6p

Selection of a Fault Model for Fault Diagnosis Based on Unique Responses.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; November 2010, Vol. 18 Issue 11, p1533-1543, 11p

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; September 2010, Vol. 29 Issue 9, p1449-1453, 5p

Switching Activity as a Test Compaction Heuristic for Transition Faults.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; September 2010, Vol. 18 Issue 9, p1357-1361, 5p

Robust Fault Models Where Undetectable Faults Imply Logic Redundancy.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; August 2010, Vol. 18 Issue 8, p1230-1234, 5p

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; July 2010, Vol. 29 Issue 7, p1135-1140, 6p

On Test Generation With Test Vector Improvement.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; March 2010, Vol. 29 Issue 3, p502-506, 5p

TOV: Sequential Test Generation by Ordering of Test Vectors.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; March 2010, Vol. 29 Issue 3, p454-465, 12p

Path Selection for Transition Path Delay Faults.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; March 2010, Vol. 18 Issue 3, p401-409, 9p

Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computers; February 2010, Vol. 59 Issue 2, p150-158, 9p

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; February 2010, Vol. 18 Issue 2, p333-337, 5p

Forward-Looking Reverse Order Fault Simulation for n-Detection Test Sets.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; September 2009, Vol. 28 Issue 9, p1424-1428, 5p

Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; March 2009, Vol. 28 Issue 3, p426-432, 7p

Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; January 2009, Vol. 28 Issue 1, p121-129, 9p

Random Test Generation With Input Cube Avoidance.

Authors: Pomeranz, Irith Reddy, Sudhakar M.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; January 2009, Vol. 17 Issue 1, p45-54, 10p