Search Results - "RISC microprocessors"

Ventana Micro debuts 32-core RISC-V processor with UCIe.

Source: XDSL News. Nov2023, Vol. 27 Issue 11, p12-13. 2p.

Design of an Intelligent Wireless Communication Module Based on ARM.

Authors: Shihe Wang Haifei Zhou

Source: International Journal of Online Engineering. 2018, Vol. 14 Issue 8, p67-79. 13p.

Subjects: Reduced instruction set computers, RISC microprocessors, Wireless communications, Data acquisition systems, Wireless sensor networks

Will RISC-V Revolutionize Computing? The open instruction set for microprocessors promises to reshape computing and introduce new, more powerful capabilities.

Authors: Greengard, Samuel

Source: Communications of the ACM. May2020, Vol. 63 Issue 5, p30-32. 3p. 1 Color Photograph.

Subjects: RISC microprocessors, Instruction set architecture, Semiconductor industry, Microprocessor design & construction, Organizational change

Register allocation and spilling using the expected distance heuristic.

Authors: Burroughs, Neil¹, inb@uvic.ca

Source: Software: Practice & Experience; Nov2016, Vol. 46 Issue 11, p1499-1523, 25p

Platform Independent 8-bit Soft-core for SoPC.

Authors: Merchant, Farhad Pujari, Shashank Patil, Manish

Source: International MultiConference of Engineers & Computer Scientists 2009; 2009, p1541-1544, 4p, 4 Diagrams, 1 Chart

Functional Tests for RISC-microprocessors.

Authors: Sharshunov, S. G.¹

Source: Automation & Remote Control. Nov2004, Vol. 65 Issue 11, p1847-1859. 13p.

Subjects: RISC microprocessors, Microprocessors, Electronic data processing, Computer input-output equipment, Remote control, Automation

Microprocessor Wars -- Where Will The Chips Fall?

Authors: Zlotnikov, Vadim Burch, Bradley D.

Source: Black Book - Microprocessor Wars - Where Will the Chips Fall?. 1993, p1-74. 73p. 3 Diagrams, 39 Charts, 24 Graphs.

THE BATTLE ROYAL IN CHIPS.

Authors: Lewis, G. Brandt, R.

Source: BusinessWeek. 11/27/89, Issue 3135, p192-198. 5p. 32 Illustrations, 2 Charts, 1 Graph.

RISC Versus CISC. (cover story)

Authors: Stahlman, Mark D.

Source: Black Book - Desktop Computer Market. 1989, p27-33. 7p. 2 Charts, 2 Graphs.

A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention.

Authors: Hiienkari, Markus Teittinen, Jukka Koskinen, Lauri et al.

Source: Journal of Low Power Electronics & Applications; 2015, Vol. 5 Issue 2, p57-68, 12p

Design and implementation of a versatile cryptographic unit for RISC processors.

Authors: Yumbul, Kazim Savaş, Erkay Kocabaş, Övünç et al.

Source: Security & Communication Networks; Jan2014, Vol. 7 Issue 1, p36-52, 17p

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks.

Authors: Magdaleno, Eduardo Rodríguez, Manuel Pérez, Fernando et al.

Source: Sensors (14248220). Jan2014, Vol. 14 Issue 1, p416-430. 15p.

An Efficient Retargetable Simulator SIM-A for ASIP DSE and Validation with RISC and VLIW based Processors.

Authors: Kumar Jain, Manoj Kumar Ranka, Gajendra

Source: International Journal of Advanced Research in Computer Science; Mar/Apr2012, Vol. 3 Issue 2, p11-22, 12p

Real time simultaneous localization and mapping: towards low-cost multiprocessor embedded systems.

Authors: Vincke, Bastien Elouardi, Abdelhafid Lambert, Alain

Source: EURASIP Journal on Embedded Systems; Feb2012, Vol. 2012 Issue 1, p1-14, 14p

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.

Authors: Abderazek, Ben Abdallah Masuda, Masashi Canedo, Arquimedes et al.

Source: Journal of Supercomputing; Sep2011, Vol. 57 Issue 3, p314-338, 25p

New Architecture for EIA-709.1 Protocol Implementation.

Authors: Su Goog Shon Soo Mi Yang Jae Jo Lee

Source: GSTF Journal on Computing; 2011, Vol. 1 Issue 2, p180-183, 4p

Reduced-Precision Redundancy on FPGAs.

Authors: Pratt, Brian Fuller, Megan Wirthlin, Michael

Source: International Journal of Reconfigurable Computing; 2011, p1-12, 12p

Experiment Centric Teaching for Reconfigurable Processors.

Authors: Lagadec, Loïc Picard, Damien Corre, Youenn et al.

Source: International Journal of Reconfigurable Computing; 2011, p1-14, 14p

Platform-Based Software Design Flow for Heterogeneous MPSoC.

Authors: Popovici, Katalin Guerin, Xavier Rousseau, Frederic et al.

Source: ACM Transactions on Embedded Computing Systems; Jul2008, Vol. 7 Issue 4, p39-39:23, 23p, 10 Diagrams, 4 Charts

Parallel Integer Optimization for Crew Scheduling.

Authors: Alefragis, Panayiotis Sanders, Peter Takkula, Tuomo et al.

Source: Annals of Operations Research; 2000, Vol. 99 Issue 1-4, p141-166, 26p, 7 Charts, 1 Graph