Search Results - "Reduced instruction set computers"

An RV32IM Processor with a Fuzzy Logic Branch Prediction Unit and Selective Execution.

Authors: Munezero, Sonia Muchuka, Nicasio Maguu Kihato, Peter Kamita

Source: Engineering, Technology & Applied Science Research; Apr2026, Vol. 16 Issue 2, p33016-33023, 8p

Chinese Chipmaker SpacemiT Gets $86 Million in Fresh Funding.

Authors: Li, Chongjing Cao, Dong

Source: Bloomberg.com. 1/14/2026, pN.PAG-N.PAG. 1p.

AIPR: An Automated Instruction-Level Patching and Rewriting Framework for Sustainable RISC-V Research.

Authors: Choi, Juhee¹

Source: Applied Sciences (2076-3417); Feb2026, Vol. 16 Issue 3, p1461, 16p

RISC-V based Cryptographic ECC-AES Hybrid Core for Secure Communications.

Authors: S., Bharath M. B., Veena

Source: Grenze International Journal of Engineering & Technology (GIJET); Jan2026, Vol. 12 Issue Part2, p1711-1718, 8p

Configurable CPU performance analysis method for specific applications.

Authors: DENG, Quan LIN, Rongzhen LUO, Li et al.

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Nov2025, Vol. 47 Issue 11, p1901-1911. 11p.

Subjects: Computer performance, Reduced instruction set computers, Hardware, Benchmark problems (Computer science), Hypothesis, Modular design

An efficient method for RISC-V memory consistency testing based on loop unrolling.

Authors: HU, Jintao XU, Xuezheng YANG, Deheng et al.

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Nov2025, Vol. 47 Issue 11, p1932-1944. 13p.

Subjects: Reduced instruction set computers, Test methods, Open source software, Integrated circuit verification, Multiprocessors, Computer performance, Program transformation, Synchronization

Towards Memory-Efficient and High-Performance Branch Prediction: The LXOR Architecture for Control Flow Optimization in Embedded and General-Purpose RISC-V Processors.

Authors: Sutar, Devendra G. Guinde, Nitesh B.

Source: Journal of Low Power Electronics & Applications; Dec2025, Vol. 15 Issue 4, p64, 34p

Research and Implementation of Performance Optimization Methods for RISC-V Level-5 Processors.

Authors: Jin, Zhiwei Hu, Tingpeng Jie, Zhiyi et al.

Source: Applied Sciences (2076-3417); Nov2025, Vol. 15 Issue 21, p11634, 19p

RISC-Based 10K+ Core Finite Difference Method Accelerator for CFD.

Authors: Gong, Yanqiong Liu, Biwei Huang, Dongchang et al.

Source: Applied Sciences (2076-3417); Jul2025, Vol. 15 Issue 13, p7283, 16p

Spike-FlexiCAS: RISC-V Processor Simulator Supporting Flexible Cache Architecture Configuration.

Authors: Han, Jinchi Wang, Zhidong Ma, Hao et al.

Source: International Journal of Software & Informatics; 2025, Vol. 15 Issue 3, p329-348, 20p

Lazy Shadow Paging Under the RISC-V Architecture.

Authors: Li, Chuandong Yi, Ran Luo, Yingwei et al.

Source: International Journal of Software & Informatics; 2025, Vol. 15 Issue 3, p349-367, 19p

Optimization Method for High-performance Libraries Targeting RISC-V Vector Extension.

Authors: Han, Liutong Zhang, Hongbin Xing, Mingjie et al.

Source: International Journal of Software & Informatics; 2025, Vol. 15 Issue 3, p369-395, 27p

Sequential Consistency Per Location Theorem Proving in RISC-V Memory Consistency Model.

Authors: Xu, Xuezheng Yang, Deheng Wang, Lu et al.

Source: International Journal of Software & Informatics; 2025, Vol. 15 Issue 3, p283-305, 23p

Hybrid Instruction Scheduling Algorithm for RISC-V VLIW Architecture.

Authors: Li, Yijin Du, Shaomin Zhao, Jiacheng et al.

Source: International Journal of Software & Informatics; 2025, Vol. 15 Issue 3, p307-328, 22p

Preface to the Special Issue on RISC-V System Software and Hardware/Software Co-design Technology.

Authors: Wu, Yanjun Xie, Tao Hou, Rui et al.

Source: International Journal of Software & Informatics; 2025, Vol. 15 Issue 3, p277-281, 5p

A comprehensive review on implementation analysis of 5-Stage pipelined RISC-V processor.

Authors: Vaishnavi, C. M. Trupti, R. Asuti, Manjunath G. et al.

Source: AIP Conference Proceedings. 2026, Vol. 3426 Issue 1, p1-6. 6p.

Evaluation of design and verification techniques for synthesizable low power 8-Bit RISC microprocessors.

Authors: Ujwal, B. S. Sanjana, H. S. Thanishka, K. et al.

Source: AIP Conference Proceedings. 2026, Vol. 3426 Issue 1, p1-8. 8p.

ANGELINA JOLIE WAS RIGHT ABOUT COMPUTERS.

Authors: Kehe, Jason (AUTHOR)

Source: Wired. May/Jun2025, Vol. 33 Issue 5, p26-33. 8p. 3 Color Photographs, 1 Cartoon or Caricature.

Subjects: Reduced instruction set computers, Instruction set architecture, Computer architecture, Personal computers, Chief marketing officers

Standard cell library based processor design using MGDI technique.

Authors: S, Shankar S, Balamurali P, Sasipriya et al.

Source: International Journal of Electronics. Mar2026, Vol. 113 Issue 3, p465-478. 14p.

Fused Dual‐Donor Design for Accelerating Reverse Intersystem Crossing Rates of Spatially Folded Through‐Space Charge Transfer Emitters.

Authors: Li, Quanwei Zhao, Haisong Li, Maoqiu et al.

Source: Angewandte Chemie International Edition. 6/24/2025, Vol. 64 Issue 26, p1-8. 8p.