Search Results - "Zapata, Emilio L."

Low-Latency Pipelined 2D and 3D CORDIC Processors.

Authors: Antelo, Elisardo Villalba, Julio Zapata, Emilio L.

Source: IEEE Transactions on Computers; March 2008, Vol. 57 Issue 3, p404-417, 14p

A Framework to Capture Dynamic Data Structures in Pointer-Based Codes.

Authors: Corbera, Francisco Asenjo, Rafael Zapata, Emilio L.

Source: IEEE Transactions on Parallel & Distributed Systems; Feb2004, Vol. 15 Issue 2, p151-166, 16p

Probabilistic Miss Equations: Evaluating Memory Hierarchy Performance.

Authors: Fraguela, Basilio B. Doallo, Ramón Zapata, Emilio L.

Source: IEEE Transactions on Computers; March 2003, Vol. 52 Issue 3, p321-336, 16p

Privatizing transactions for Lee’s algorithm in commercial hardware transactional memory.

Authors: Quislant, Ricardo Gutierrez, Eladio Zapata, Emilio L. et al.

Source: Journal of Supercomputing; Apr2018, Vol. 74 Issue 4, p1676-1694, 19p

Unified mixed radix 2-4 redundant CORDIC processor.

Authors: Antelo, Elisardo Bruguera, Javier D. Zapata, Emilio L.

Source: IEEE Transactions on Computers; September 1996, Vol. 45, p1068-1073, 6p

Unified architecture for divide and conquer based tridiagonal system solvers.

Authors: López, Juan Zapata, Emilio L.

Source: IEEE Transactions on Computers; December 1994, Vol. 43, p1413-1425, 13p

Vienna-Fortran/HPF extensions for sparse and irregular problems and their compilation.

Authors: Ujaldon, Manuel Zapata, Emilio L. Chapman, Barbara M.

Source: IEEE Transactions on Parallel & Distributed Systems; October 1997, Vol. 8, p1068-1083, 16p

A VLSI constant geometry architecture for the fast Hartley and Fourier transforms.

Authors: Zapata, Emilio L. Argüello, F.

Source: IEEE Transactions on Parallel & Distributed Systems; January 1992, Vol. 3, p58-70, 13p

INTEROPERABLE DIGITAL MEDIA ECOSYSTEMS.

Authors: Zapata, Emilio L.¹

Source: TVB Europe. Nov/Dec2021, pII-III. 2p.

ADOPTION OF MEDIA-CENTRIC iPaaS IN MEDIA AND ENTERTAINMENT.

Authors: Zapata, Emilio L.¹

Source: TVB Europe. Nov/Dec2020, pII-III. 2p.

THE NEXT GENERATION OF MAM.

Authors: Zapata, Emilio L.

Source: TVB Europe. Jul/Aug2020, p40-41. 2p.

Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions.

Authors: Quislant, Ricardo Gutierrez, Eladio Zapata, Emilio L. et al.

Source: Journal of Parallel & Distributed Computing; Sep2019, Vol. 131, p103-119, 17p

SHAPING THE MEDIA FACTORY TECHNOLOGY.

Authors: Zapata, Emilio L.

Source: TVB Europe. Nov/Dec2019, pII-III. 2p.

TAKING A RADICAL VIEW OF THE MEDIA FUTURE.

Authors: Zapata, Emilio L.¹

Source: TVB Europe. Nov/Dec2018, pII-III. 2p.

Lazy Irrevocability for Best-Effort Transactional Memory Systems.

Authors: Quislant, Ricardo Gutierrez, Eladio Zapata, Emilio L. et al.

Source: IEEE Transactions on Parallel & Distributed Systems; Jul2017, Vol. 28 Issue 7, p1919-1932, 14p

Enhancing scalability in best-effort hardware transactional memory systems.

Authors: Quislant, Ricardo Gutierrez, Eladio Zapata, Emilio L. et al.

Source: Journal of Parallel & Distributed Computing; Jun2017, Vol. 104, p73-87, 15p

A case study of different task implementations for multioutput stages in non-trivial parallel pipeline applications.

Authors: Navarro, Angeles Asenjo, Rafael Corbera, Francisco et al.

Source: Parallel Computing; Aug2014, Vol. 40 Issue 8, p374-393, 20p

Multioperand Redundant Adders on FPGAs.

Authors: Hormigo, Javier Villalba, Julio Zapata, Emilio L.

Source: IEEE Transactions on Computers; Oct2013, Vol. 62 Issue 10, p2013-2025, 13p

Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets.

Authors: Quislant, Ricardo Gutierrez, Eladio Plata, Oscar et al.

Source: IEEE Transactions on Parallel & Distributed Systems; Mar2013, Vol. 24 Issue 3, p506-519, 14p

LS-Sig: Locality-Sensitive Signatures for Transactional Memory.

Authors: Quislant, Ricardo Gutiérrez, Eladio Plata, Oscar et al.

Source: IEEE Transactions on Computers; Feb2013, Vol. 62 Issue 2, p322-335, 14p