APA (7th ed.) Citation

Hameed, F., Bauer, L., & Henkel, J. (2014). Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. DAC: Annual ACM/IEEE Design Automation Conference, 209. https://doi.org/10.1145/2593069.2593197

Chicago Style (17th ed.) Citation

Hameed, Fazal, Lars Bauer, and Jörg Henkel. "Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture." DAC: Annual ACM/IEEE Design Automation Conference 2014: 209. https://doi.org/10.1145/2593069.2593197.

MLA (9th ed.) Citation

Hameed, Fazal, et al. "Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture." DAC: Annual ACM/IEEE Design Automation Conference, 2014, p. 209, https://doi.org/10.1145/2593069.2593197.