Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.
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| Title: | Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. |
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| Authors: | Hameed, Fazal1, hameed@kit.edu, Bauer, Lars1, lars.bauer@kit.edu, Henkel, Jörg1, henkel@kit.edu |
| Source: | DAC: Annual ACM/IEEE Design Automation Conference; 2014, p209-214, 6p |
| Database: | Applied Science & Technology Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 108916710 AccessLevel: 2 PubType: Conference PubTypeId: conference PreciseRelevancyScore: 0 |
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| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=108916710 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1145/2593069.2593197 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 6 StartPage: 209 Titles: – TitleFull: Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Hameed, Fazal – PersonEntity: Name: NameFull: Bauer, Lars – PersonEntity: Name: NameFull: Henkel, Jörg IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: 2014 Type: published Y: 2014 Identifiers: – Type: issn-print Value: 0738100X Titles: – TitleFull: DAC: Annual ACM/IEEE Design Automation Conference Type: main |
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