Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.
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| Title: | Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. |
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| Authors: | Hameed, Fazal1, hameed@kit.edu, Bauer, Lars1, lars.bauer@kit.edu, Henkel, Jörg1, henkel@kit.edu |
| Source: | DAC: Annual ACM/IEEE Design Automation Conference; 2014, p209-214, 6p |
| Database: | Applied Science & Technology Source |
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