APA (7th ed.) Citation

Said, M., Shalaby, A., Mehdipour, F., Biglari-Abhari, M., & El-Sayed, M. (2016). A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias. Microprocessors & Microsystems, 43, 26. https://doi.org/10.1016/j.micpro.2016.01.011

Chicago Style (17th ed.) Citation

Said, Mostafa, Ahmed Shalaby, Farhad Mehdipour, Morteza Biglari-Abhari, and Mohamed El-Sayed. "A Design Methodology and Various Performance and Fabrication Metrics Evaluation of 3D Network-on-Chip with Multiplexed Through-Silicon Vias." Microprocessors & Microsystems 43 (2016): 26. https://doi.org/10.1016/j.micpro.2016.01.011.

MLA (9th ed.) Citation

Said, Mostafa, et al. "A Design Methodology and Various Performance and Fabrication Metrics Evaluation of 3D Network-on-Chip with Multiplexed Through-Silicon Vias." Microprocessors & Microsystems, vol. 43, 2016, p. 26, https://doi.org/10.1016/j.micpro.2016.01.011.