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A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.

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Title: A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.
Authors: Said, Mostafa1, mostafa.saied@ejust.edu.eg, Shalaby, Ahmed2, ahmed.shalaby@ejust.edu.eg, Mehdipour, Farhad3, farhad@ejust.kyushu-u.ac.jp, Biglari-Abhari, Morteza4, m.abhari@auckland.ac.nz, El-Sayed, Mohamed2, m.ragab@ejust.edu.eg
Source: Microprocessors & Microsystems; Jun2016, Vol. 43, p26-46, 21p
Database: Applied Science & Technology Source
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  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 115366983
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.
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PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=115366983
RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1016/j.micpro.2016.01.011
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      – Code: eng
        Text: English
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        PageCount: 21
        StartPage: 26
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      – TitleFull: A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.
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          Name:
            NameFull: Said, Mostafa
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            NameFull: Shalaby, Ahmed
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            NameFull: Mehdipour, Farhad
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            NameFull: Biglari-Abhari, Morteza
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            NameFull: El-Sayed, Mohamed
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            – D: 01
              M: 06
              Text: Jun2016
              Type: published
              Y: 2016
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              Value: 01419331
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              Value: 43
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