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A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.

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Bibliographic Details
Title: A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.
Authors: Said, Mostafa1, mostafa.saied@ejust.edu.eg, Shalaby, Ahmed2, ahmed.shalaby@ejust.edu.eg, Mehdipour, Farhad3, farhad@ejust.kyushu-u.ac.jp, Biglari-Abhari, Morteza4, m.abhari@auckland.ac.nz, El-Sayed, Mohamed2, m.ragab@ejust.edu.eg
Source: Microprocessors & Microsystems; Jun2016, Vol. 43, p26-46, 21p
Database: Applied Science & Technology Source
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