APA (7th ed.) Citation

Cheng, M., Xia, L., Zhu, Z., Cai, Y., Xie, Y., Wang, Y., & Yang, H. (2017). TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks. DAC: Annual ACM/IEEE Design Automation Conference, 54, 297. https://doi.org/10.1145/3061639.3062326

Chicago Style (17th ed.) Citation

Cheng, Ming, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, and Huazhong Yang. "TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks." DAC: Annual ACM/IEEE Design Automation Conference 54 (2017): 297. https://doi.org/10.1145/3061639.3062326.

MLA (9th ed.) Citation

Cheng, Ming, et al. "TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks." DAC: Annual ACM/IEEE Design Automation Conference, 54, 2017, p. 297, https://doi.org/10.1145/3061639.3062326.