APA (7th ed.) Citation

Zhao, Q., Liu, Y., Sun, W., Zhao, J., Yao, H., Guo, X., & Yang, H. (2017). Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. DAC: Annual ACM/IEEE Design Automation Conference, 54, 939. https://doi.org/10.1145/3061639.3062227

Chicago Style (17th ed.) Citation

Zhao, Qinghang, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, and Huazhong Yang. "Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture." DAC: Annual ACM/IEEE Design Automation Conference 54 (2017): 939. https://doi.org/10.1145/3061639.3062227.

MLA (9th ed.) Citation

Zhao, Qinghang, et al. "Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture." DAC: Annual ACM/IEEE Design Automation Conference, 54, 2017, p. 939, https://doi.org/10.1145/3061639.3062227.