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Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

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Title: Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
Authors: Qinghang Zhao1, Yongpan Liu1, ypliu@tsinghua.edu.cn, Wenyu Sun1, Jiaqing Zhao2, Hailong Yao1, Xiaojun Guo2, x.guo@sjtu.edu.cn, Huazhong Yang1
Source: DAC: Annual ACM/IEEE Design Automation Conference; 2017, Issue 54, p939-944, 6p
Database: Applied Science & Technology Source
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DbLabel: Applied Science & Technology Source
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PubType: Conference
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  Data: Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
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      – Type: doi
        Value: 10.1145/3061639.3062227
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      – Code: eng
        Text: English
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      – TitleFull: Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
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            NameFull: Qinghang Zhao
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            NameFull: Yongpan Liu
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            NameFull: Wenyu Sun
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            NameFull: Jiaqing Zhao
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            NameFull: Hailong Yao
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            NameFull: Xiaojun Guo
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            NameFull: Huazhong Yang
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            – D: 01
              M: 01
              Text: 2017
              Type: published
              Y: 2017
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