Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
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| Title: | Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. |
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| Authors: | Qinghang Zhao1, Yongpan Liu1, ypliu@tsinghua.edu.cn, Wenyu Sun1, Jiaqing Zhao2, Hailong Yao1, Xiaojun Guo2, x.guo@sjtu.edu.cn, Huazhong Yang1 |
| Source: | DAC: Annual ACM/IEEE Design Automation Conference; 2017, Issue 54, p939-944, 6p |
| Database: | Applied Science & Technology Source |
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