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Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.

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Title: Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.
Authors: Silveira, Bianca1, Paim, Guilherme2, Abreu, Brunno2, Grellert, Mateus2, Diniz, Claudio Machado1, da Costa, Eduardo Antonio Cesar1, Bampi, Sergio2
Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Dec2017, Vol. 64 Issue 12, p3126-3137, 12p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 126469662
AccessLevel: 2
PubType: Periodical
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        Value: 10.1109/TCSI.2017.2728802
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        Text: English
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              Text: Dec2017
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