Grasso, A. D., Marano, D., Palumbo, G., & Pennisi, S. (2018). High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of ${C}_{L}$. IEEE Transactions on Circuits & Systems. Part II: Express Briefs, 65(11), 1529. https://doi.org/10.1109/TCSII.2017.2756923
Chicago Style (17th ed.) CitationGrasso, Alfio Dario, D. Marano, G. Palumbo, and S. Pennisi. "High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of ${C}_{L}$." IEEE Transactions on Circuits & Systems. Part II: Express Briefs 65, no. 11 (2018): 1529. https://doi.org/10.1109/TCSII.2017.2756923.
MLA (9th ed.) CitationGrasso, Alfio Dario, et al. "High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of ${C}_{L}$." IEEE Transactions on Circuits & Systems. Part II: Express Briefs, vol. 65, no. 11, 2018, p. 1529, https://doi.org/10.1109/TCSII.2017.2756923.