APA (7th ed.) Citation

Hasan, M., Hossein, M. J., Hossain, M., Zaman, H. U., & Islam, S. (2020). Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation. IEEE Transactions on Circuits & Systems. Part II: Express Briefs, 67(8), 1464. https://doi.org/10.1109/TCSII.2019.2940558

Chicago Style (17th ed.) Citation

Hasan, Mehedi, Md. Jobayer Hossein, Mainul Hossain, Hasan U. Zaman, and Sharnali Islam. "Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation." IEEE Transactions on Circuits & Systems. Part II: Express Briefs 67, no. 8 (2020): 1464. https://doi.org/10.1109/TCSII.2019.2940558.

MLA (9th ed.) Citation

Hasan, Mehedi, et al. "Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation." IEEE Transactions on Circuits & Systems. Part II: Express Briefs, vol. 67, no. 8, 2020, p. 1464, https://doi.org/10.1109/TCSII.2019.2940558.