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Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.

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Title: Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.
Authors: Hasan, Mehedi1, mehedi.hasan01@northsouth.edu, Hossein, Md. Jobayer1, jobayerhossein@gmail.com, Hossain, Mainul2, mainul.eee@du.ac.bd, Zaman, Hasan U.1, hasan.zaman@northsouth.edu, Islam, Sharnali3, sharnali.eee@du.ac.bd
Source: IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Aug2020, Vol. 67 Issue 8, p1464-1468, 5p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 144890754
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AU" term="%22Hasan%2C+Mehedi%22">Hasan, Mehedi</searchLink><relatesTo>1</relatesTo>, <i>mehedi.hasan01@northsouth.edu</i><br /><searchLink fieldCode="AU" term="%22Hossein%2C+Md%2E+Jobayer%22">Hossein, Md. Jobayer</searchLink><relatesTo>1</relatesTo>, <i>jobayerhossein@gmail.com</i><br /><searchLink fieldCode="AU" term="%22Hossain%2C+Mainul%22">Hossain, Mainul</searchLink><relatesTo>2</relatesTo>, <i>mainul.eee@du.ac.bd</i><br /><searchLink fieldCode="AU" term="%22Zaman%2C+Hasan+U%2E%22">Zaman, Hasan U.</searchLink><relatesTo>1</relatesTo>, <i>hasan.zaman@northsouth.edu</i><br /><searchLink fieldCode="AU" term="%22Islam%2C+Sharnali%22">Islam, Sharnali</searchLink><relatesTo>3</relatesTo>, <i>sharnali.eee@du.ac.bd</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Circuits+%26+Systems%2E+Part+II%3A+Express+Briefs%22">IEEE Transactions on Circuits & Systems. Part II: Express Briefs</searchLink>; Aug2020, Vol. 67 Issue 8, p1464-1468, 5p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=144890754
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/TCSII.2019.2940558
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 5
        StartPage: 1464
    Titles:
      – TitleFull: Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Hasan, Mehedi
      – PersonEntity:
          Name:
            NameFull: Hossein, Md. Jobayer
      – PersonEntity:
          Name:
            NameFull: Hossain, Mainul
      – PersonEntity:
          Name:
            NameFull: Zaman, Hasan U.
      – PersonEntity:
          Name:
            NameFull: Islam, Sharnali
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 08
              Text: Aug2020
              Type: published
              Y: 2020
          Identifiers:
            – Type: issn-print
              Value: 15497747
          Numbering:
            – Type: volume
              Value: 67
            – Type: issue
              Value: 8
          Titles:
            – TitleFull: IEEE Transactions on Circuits & Systems. Part II: Express Briefs
              Type: main
ResultId 1