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Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.

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Bibliographic Details
Title: Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.
Authors: Hasan, Mehedi1, mehedi.hasan01@northsouth.edu, Hossein, Md. Jobayer1, jobayerhossein@gmail.com, Hossain, Mainul2, mainul.eee@du.ac.bd, Zaman, Hasan U.1, hasan.zaman@northsouth.edu, Islam, Sharnali3, sharnali.eee@du.ac.bd
Source: IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Aug2020, Vol. 67 Issue 8, p1464-1468, 5p
Database: Applied Science & Technology Source
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