APA (7th ed.) Citation

Dhar, A., Richter, E., Yu, M., Zuo, W., Wang, X., Kim, N. S., & Chen, D. (2022). DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs. IEEE Transactions on Computers, 71(10), 2577. https://doi.org/10.1109/TC.2021.3137785

Chicago Style (17th ed.) Citation

Dhar, Ashutosh, Edward Richter, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, and Deming Chen. "DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs." IEEE Transactions on Computers 71, no. 10 (2022): 2577. https://doi.org/10.1109/TC.2021.3137785.

MLA (9th ed.) Citation

Dhar, Ashutosh, et al. "DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs." IEEE Transactions on Computers, vol. 71, no. 10, 2022, p. 2577, https://doi.org/10.1109/TC.2021.3137785.