DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.
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| Title: | DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs. |
|---|---|
| Authors: | Dhar, Ashutosh1, adhar2@illinois.edu, Richter, Edward1, edwardr2@illinois.edu, Yu, Mang1, mangyu2@illinois.edu, Zuo, Wei1, weizuo@illinois.edu, Wang, Xiaohao1, xwang165@illinois.edu, Kim, Nam Sung1, nskim@illinois.edu, Chen, Deming1, dchen@illinois.edu |
| Source: | IEEE Transactions on Computers; Oct2022, Vol. 71 Issue 10, p2577-2591, 15p |
| Database: | Applied Science & Technology Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 159041223 AccessLevel: 2 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AU" term="%22Dhar%2C+Ashutosh%22">Dhar, Ashutosh</searchLink><relatesTo>1</relatesTo>, <i>adhar2@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Richter%2C+Edward%22">Richter, Edward</searchLink><relatesTo>1</relatesTo>, <i>edwardr2@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Yu%2C+Mang%22">Yu, Mang</searchLink><relatesTo>1</relatesTo>, <i>mangyu2@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Zuo%2C+Wei%22">Zuo, Wei</searchLink><relatesTo>1</relatesTo>, <i>weizuo@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Wang%2C+Xiaohao%22">Wang, Xiaohao</searchLink><relatesTo>1</relatesTo>, <i>xwang165@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Kim%2C+Nam+Sung%22">Kim, Nam Sung</searchLink><relatesTo>1</relatesTo>, <i>nskim@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Chen%2C+Deming%22">Chen, Deming</searchLink><relatesTo>1</relatesTo>, <i>dchen@illinois.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>; Oct2022, Vol. 71 Issue 10, p2577-2591, 15p |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=159041223 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TC.2021.3137785 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 15 StartPage: 2577 Titles: – TitleFull: DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Dhar, Ashutosh – PersonEntity: Name: NameFull: Richter, Edward – PersonEntity: Name: NameFull: Yu, Mang – PersonEntity: Name: NameFull: Zuo, Wei – PersonEntity: Name: NameFull: Wang, Xiaohao – PersonEntity: Name: NameFull: Kim, Nam Sung – PersonEntity: Name: NameFull: Chen, Deming IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2022 Type: published Y: 2022 Identifiers: – Type: issn-print Value: 00189340 Numbering: – Type: volume Value: 71 – Type: issue Value: 10 Titles: – TitleFull: IEEE Transactions on Computers Type: main |
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