DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.

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Title: DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.
Authors: Dhar, Ashutosh1, adhar2@illinois.edu, Richter, Edward1, edwardr2@illinois.edu, Yu, Mang1, mangyu2@illinois.edu, Zuo, Wei1, weizuo@illinois.edu, Wang, Xiaohao1, xwang165@illinois.edu, Kim, Nam Sung1, nskim@illinois.edu, Chen, Deming1, dchen@illinois.edu
Source: IEEE Transactions on Computers; Oct2022, Vol. 71 Issue 10, p2577-2591, 15p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 159041223
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.
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  Data: <searchLink fieldCode="AU" term="%22Dhar%2C+Ashutosh%22">Dhar, Ashutosh</searchLink><relatesTo>1</relatesTo>, <i>adhar2@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Richter%2C+Edward%22">Richter, Edward</searchLink><relatesTo>1</relatesTo>, <i>edwardr2@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Yu%2C+Mang%22">Yu, Mang</searchLink><relatesTo>1</relatesTo>, <i>mangyu2@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Zuo%2C+Wei%22">Zuo, Wei</searchLink><relatesTo>1</relatesTo>, <i>weizuo@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Wang%2C+Xiaohao%22">Wang, Xiaohao</searchLink><relatesTo>1</relatesTo>, <i>xwang165@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Kim%2C+Nam+Sung%22">Kim, Nam Sung</searchLink><relatesTo>1</relatesTo>, <i>nskim@illinois.edu</i><br /><searchLink fieldCode="AU" term="%22Chen%2C+Deming%22">Chen, Deming</searchLink><relatesTo>1</relatesTo>, <i>dchen@illinois.edu</i>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>; Oct2022, Vol. 71 Issue 10, p2577-2591, 15p
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1109/TC.2021.3137785
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      – Code: eng
        Text: English
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        PageCount: 15
        StartPage: 2577
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      – TitleFull: DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.
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            NameFull: Wang, Xiaohao
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            NameFull: Kim, Nam Sung
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            NameFull: Chen, Deming
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            – D: 01
              M: 10
              Text: Oct2022
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              Y: 2022
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