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DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.

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Bibliographic Details
Title: DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.
Authors: Dhar, Ashutosh1, adhar2@illinois.edu, Richter, Edward1, edwardr2@illinois.edu, Yu, Mang1, mangyu2@illinois.edu, Zuo, Wei1, weizuo@illinois.edu, Wang, Xiaohao1, xwang165@illinois.edu, Kim, Nam Sung1, nskim@illinois.edu, Chen, Deming1, dchen@illinois.edu
Source: IEEE Transactions on Computers; Oct2022, Vol. 71 Issue 10, p2577-2591, 15p
Database: Applied Science & Technology Source
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