APA (7th ed.) Citation

Chandrasekharan, R., & Prasad, S. N. (2025). Fault tolerant design for 8-bit Dadda multiplier for neural network applications. International Journal of Electrical & Computer Engineering (2088-8708), 15(3), 1. https://doi.org/10.11591/ijece.v15i3.pp2697-2705

Chicago Style (17th ed.) Citation

Chandrasekharan, Raji, and Sarappadi Narasimha Prasad. "Fault Tolerant Design for 8-bit Dadda Multiplier for Neural Network Applications." International Journal of Electrical & Computer Engineering (2088-8708) 15, no. 3 (2025): 1. https://doi.org/10.11591/ijece.v15i3.pp2697-2705.

MLA (9th ed.) Citation

Chandrasekharan, Raji, and Sarappadi Narasimha Prasad. "Fault Tolerant Design for 8-bit Dadda Multiplier for Neural Network Applications." International Journal of Electrical & Computer Engineering (2088-8708), vol. 15, no. 3, 2025, p. 1, https://doi.org/10.11591/ijece.v15i3.pp2697-2705.