APA (7th ed.) Citation

Cardoso, G. B., Huarachi, H. M. C., Tomm, D. F., Gomes, J. S., Würdig, R. N., de Moraes, M. R., . . . Ramos, F. L. L. (2025). Hardware accelerator for VVC/H.266 residual syntax elements: A unified and resource-efficient architecture. Journal of Real-Time Image Processing, 22(4), 1. https://doi.org/10.1007/s11554-025-01733-8

Chicago Style (17th ed.) Citation

Cardoso, Gabriel Bitencourt, Heitor Mauro Chavez Huarachi, Daniel Felipe Tomm, Jiovana Sousa Gomes, Rodrigo Nogueira Würdig, Marcelo Romero de Moraes, Sergio Bampi, and Fábio Luís Livi Ramos. "Hardware Accelerator for VVC/H.266 Residual Syntax Elements: A Unified and Resource-efficient Architecture." Journal of Real-Time Image Processing 22, no. 4 (2025): 1. https://doi.org/10.1007/s11554-025-01733-8.

MLA (9th ed.) Citation

Cardoso, Gabriel Bitencourt, et al. "Hardware Accelerator for VVC/H.266 Residual Syntax Elements: A Unified and Resource-efficient Architecture." Journal of Real-Time Image Processing, vol. 22, no. 4, 2025, p. 1, https://doi.org/10.1007/s11554-025-01733-8.