Hardware accelerator for VVC/H.266 residual syntax elements: a unified and resource-efficient architecture.

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Title: Hardware accelerator for VVC/H.266 residual syntax elements: a unified and resource-efficient architecture.
Authors: Cardoso, Gabriel Bitencourt1, gabrielbc.aluno@unipampa.edu.br, Huarachi, Heitor Mauro Chavez1, heitorhuarachi.aluno@unipampa.edu.br, Tomm, Daniel Felipe1, danieltomm.aluno@unipampa.edu.br, Gomes, Jiovana Sousa2, jsgomes@inf.ufrgs.br, Würdig, Rodrigo Nogueira2, rnwurdig@inf.ufrgs.br, de Moraes, Marcelo Romero1, marceloromero@unipampa.edu.br, Bampi, Sergio2, bampi@inf.ufrgs.br, Ramos, Fábio Luís Livi1, fabioramos@unipampa.edu.br
Source: Journal of Real-Time Image Processing; Aug2025, Vol. 22 Issue 4, p1-14, 14p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 186847977
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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      – Type: doi
        Value: 10.1007/s11554-025-01733-8
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      – Code: eng
        Text: English
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        PageCount: 14
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            NameFull: Cardoso, Gabriel Bitencourt
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            NameFull: Huarachi, Heitor Mauro Chavez
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            NameFull: Tomm, Daniel Felipe
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            NameFull: de Moraes, Marcelo Romero
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            – D: 01
              M: 08
              Text: Aug2025
              Type: published
              Y: 2025
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              Value: 22
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