Hardware accelerator for VVC/H.266 residual syntax elements: a unified and resource-efficient architecture.
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| Title: | Hardware accelerator for VVC/H.266 residual syntax elements: a unified and resource-efficient architecture. |
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| Authors: | Cardoso, Gabriel Bitencourt1, gabrielbc.aluno@unipampa.edu.br, Huarachi, Heitor Mauro Chavez1, heitorhuarachi.aluno@unipampa.edu.br, Tomm, Daniel Felipe1, danieltomm.aluno@unipampa.edu.br, Gomes, Jiovana Sousa2, jsgomes@inf.ufrgs.br, Würdig, Rodrigo Nogueira2, rnwurdig@inf.ufrgs.br, de Moraes, Marcelo Romero1, marceloromero@unipampa.edu.br, Bampi, Sergio2, bampi@inf.ufrgs.br, Ramos, Fábio Luís Livi1, fabioramos@unipampa.edu.br |
| Source: | Journal of Real-Time Image Processing; Aug2025, Vol. 22 Issue 4, p1-14, 14p |
| Database: | Applied Science & Technology Source |
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