APA (7th ed.) Citation

Meng, X., Ji, X., Zhang, G., He, J., Yang, D., Chen, F., . . . Wu, J. (2025). Rtl design flaws revisited: A data-driven study of systematic bug patterns in Verilog code. Journal of Supercomputing, 81(14), 1. https://doi.org/10.1007/s11227-025-07811-9

Chicago Style (17th ed.) Citation

Meng, Xiankai, et al. "Rtl Design Flaws Revisited: A Data-driven Study of Systematic Bug Patterns in Verilog Code." Journal of Supercomputing 81, no. 14 (2025): 1. https://doi.org/10.1007/s11227-025-07811-9.

MLA (9th ed.) Citation

Meng, Xiankai, et al. "Rtl Design Flaws Revisited: A Data-driven Study of Systematic Bug Patterns in Verilog Code." Journal of Supercomputing, vol. 81, no. 14, 2025, p. 1, https://doi.org/10.1007/s11227-025-07811-9.