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Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code.

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Title: Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code.
Authors: Meng, Xiankai1, xkmeng@sspu.edu.cn, Ji, Xiang1, jixiang11730@yeah.net, Zhang, Guangda2, zhanggd_nudt@hotmail.com, He, Jiayu3, hejy47@nudt.edu.cn, Yang, Deheng2, dehengyang@outlook.com, Chen, Fangshu1, fschen@sspu.edu.cn, Wang, Jiahui1, wangjh@sspu.edu.cn, Yu, Chengcheng1, ccyu@sspu.edu.cn, Zhao, Xinlin4, xinlin.zhao.asu@gmail.com, Wu, Jiang2, wujadeon@outlook.com
Source: Journal of Supercomputing; Sep2025, Vol. 81 Issue 14, p1-32, 32p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 187855102
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code.
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  Data: <searchLink fieldCode="AU" term="%22Meng%2C+Xiankai%22">Meng, Xiankai</searchLink><relatesTo>1</relatesTo>, <i>xkmeng@sspu.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Ji%2C+Xiang%22">Ji, Xiang</searchLink><relatesTo>1</relatesTo>, <i>jixiang11730@yeah.net</i><br /><searchLink fieldCode="AU" term="%22Zhang%2C+Guangda%22">Zhang, Guangda</searchLink><relatesTo>2</relatesTo>, <i>zhanggd_nudt@hotmail.com</i><br /><searchLink fieldCode="AU" term="%22He%2C+Jiayu%22">He, Jiayu</searchLink><relatesTo>3</relatesTo>, <i>hejy47@nudt.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Yang%2C+Deheng%22">Yang, Deheng</searchLink><relatesTo>2</relatesTo>, <i>dehengyang@outlook.com</i><br /><searchLink fieldCode="AU" term="%22Chen%2C+Fangshu%22">Chen, Fangshu</searchLink><relatesTo>1</relatesTo>, <i>fschen@sspu.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Wang%2C+Jiahui%22">Wang, Jiahui</searchLink><relatesTo>1</relatesTo>, <i>wangjh@sspu.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Yu%2C+Chengcheng%22">Yu, Chengcheng</searchLink><relatesTo>1</relatesTo>, <i>ccyu@sspu.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Zhao%2C+Xinlin%22">Zhao, Xinlin</searchLink><relatesTo>4</relatesTo>, <i>xinlin.zhao.asu@gmail.com</i><br /><searchLink fieldCode="AU" term="%22Wu%2C+Jiang%22">Wu, Jiang</searchLink><relatesTo>2</relatesTo>, <i>wujadeon@outlook.com</i>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>; Sep2025, Vol. 81 Issue 14, p1-32, 32p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=187855102
RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1007/s11227-025-07811-9
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      – Code: eng
        Text: English
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        PageCount: 32
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      – TitleFull: Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code.
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            NameFull: Meng, Xiankai
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            NameFull: Ji, Xiang
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            NameFull: Zhang, Guangda
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            NameFull: Zhao, Xinlin
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            – D: 15
              M: 09
              Text: Sep2025
              Type: published
              Y: 2025
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              Value: 09208542
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              Value: 81
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              Value: 14
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            – TitleFull: Journal of Supercomputing
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