Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code. - Meng, Xiankai; Ji, Xiang; Zhang, Guangda; He, Jiayu; Yang, Deheng; Chen, Fangshu; Wang, Jiahui; Yu, Chengcheng; Zhao, Xinlin; Wu, Jiang (Journal of Supercomputing, 2025)