Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code.
Saved in:
| Title: | Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code. |
|---|---|
| Authors: | Meng, Xiankai1, xkmeng@sspu.edu.cn, Ji, Xiang1, jixiang11730@yeah.net, Zhang, Guangda2, zhanggd_nudt@hotmail.com, He, Jiayu3, hejy47@nudt.edu.cn, Yang, Deheng2, dehengyang@outlook.com, Chen, Fangshu1, fschen@sspu.edu.cn, Wang, Jiahui1, wangjh@sspu.edu.cn, Yu, Chengcheng1, ccyu@sspu.edu.cn, Zhao, Xinlin4, xinlin.zhao.asu@gmail.com, Wu, Jiang2, wujadeon@outlook.com |
| Source: | Journal of Supercomputing; Sep2025, Vol. 81 Issue 14, p1-32, 32p |
| Database: | Applied Science & Technology Source |
Be the first to leave a comment!
