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OpenCL-accelerated FPGA for real-time AES-128 signal encryption and decryption.

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Title: OpenCL-accelerated FPGA for real-time AES-128 signal encryption and decryption.
Authors: Firmansyah, Iman1, iman006@brin.go.id, Setiadi, Bambang1, Suyoto, Suyoto1, Prini, Salita Ulitia1, Indrawijaya, Ratna1, Rohman, Budiman P.A.1, Yamaguchi, Yoshiki2,3
Source: AEU: International Journal of Electronics & Communications; Feb2026, Vol. 206, pN.PAG-N.PAG, 1p
Database: Applied Science & Technology Source
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  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 191143754
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: OpenCL-accelerated FPGA for real-time AES-128 signal encryption and decryption.
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  Data: <searchLink fieldCode="JN" term="%22AEU%3A+International+Journal+of+Electronics+%26+Communications%22">AEU: International Journal of Electronics & Communications</searchLink>; Feb2026, Vol. 206, pN.PAG-N.PAG, 1p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=191143754
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1016/j.aeue.2025.156187
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      – Code: eng
        Text: English
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        PageCount: 1
        StartPage: N.PAG
    Titles:
      – TitleFull: OpenCL-accelerated FPGA for real-time AES-128 signal encryption and decryption.
        Type: main
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      – PersonEntity:
          Name:
            NameFull: Firmansyah, Iman
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            NameFull: Setiadi, Bambang
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            NameFull: Suyoto, Suyoto
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            NameFull: Prini, Salita Ulitia
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            NameFull: Indrawijaya, Ratna
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            NameFull: Rohman, Budiman P.A.
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            NameFull: Yamaguchi, Yoshiki
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            – D: 15
              M: 02
              Text: Feb2026
              Type: published
              Y: 2026
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              Value: 206
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            – TitleFull: AEU: International Journal of Electronics & Communications
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