APA (7th ed.) Citation

CHANDRASEKHAR, C., DAS, S. M., JAYACHANDRANATH, S., FARUK, S. K. U., JAYAPRAKASAN, V., & BASHA, M. M. (2025). Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing. Journal of Active & Passive Electronic Devices, 19(4), 301.

Chicago Style (17th ed.) Citation

CHANDRASEKHAR, CHAKALI, SARI MOHAN DAS, S. JAYACHANDRANATH, S. K. UMAR FARUK, V. JAYAPRAKASAN, and MOHAMMED MAHABOOB BASHA. "Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing." Journal of Active & Passive Electronic Devices 19, no. 4 (2025): 301.

MLA (9th ed.) Citation

CHANDRASEKHAR, CHAKALI, et al. "Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing." Journal of Active & Passive Electronic Devices, vol. 19, no. 4, 2025, p. 301.