Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing.
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| Title: | Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing. |
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| Authors: | CHANDRASEKHAR, CHAKALI1, DAS, SARI MOHAN2, JAYACHANDRANATH, S.2, FARUK, S. K. UMAR3, JAYAPRAKASAN, V.4, BASHA, MOHAMMED MAHABOOB4, mmehboobbasha@gmail.com |
| Source: | Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p301-312, 12p |
| Database: | Applied Science & Technology Source |
| ISSN: | 15550281 |
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