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Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing.

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Title: Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing.
Authors: CHANDRASEKHAR, CHAKALI1, DAS, SARI MOHAN2, JAYACHANDRANATH, S.2, FARUK, S. K. UMAR3, JAYAPRAKASAN, V.4, BASHA, MOHAMMED MAHABOOB4, mmehboobbasha@gmail.com
Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p301-312, 12p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 191623199
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing.
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Active+%26+Passive+Electronic+Devices%22">Journal of Active & Passive Electronic Devices</searchLink>; 2025, Vol. 19 Issue 4, p301-312, 12p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=191623199
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      – Code: eng
        Text: English
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        PageCount: 12
        StartPage: 301
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      – TitleFull: Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing.
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            NameFull: CHANDRASEKHAR, CHAKALI
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            NameFull: DAS, SARI MOHAN
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            NameFull: JAYACHANDRANATH, S.
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            NameFull: FARUK, S. K. UMAR
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            NameFull: JAYAPRAKASAN, V.
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            NameFull: BASHA, MOHAMMED MAHABOOB
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            – D: 01
              M: 12
              Text: 2025
              Type: published
              Y: 2025
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              Value: 19
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            – TitleFull: Journal of Active & Passive Electronic Devices
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