APA (7th ed.) Citation

T., H., Gupta, K. A., G., P., & Ninawe, S. S. (2026). Power Efficient Memory based Transistor-Memristor with CMOS Configuration Hybrid Mode Circuits for Future Neuromorphic Computation. Grenze International Journal of Engineering & Technology (GIJET), 12(Part2), 4115.

Chicago Style (17th ed.) Citation

T., Harish, Kiran A. Gupta, Pavithra G., and Swapnil S. Ninawe. "Power Efficient Memory Based Transistor-Memristor with CMOS Configuration Hybrid Mode Circuits for Future Neuromorphic Computation." Grenze International Journal of Engineering & Technology (GIJET) 12, no. Part2 (2026): 4115.

MLA (9th ed.) Citation

T., Harish, et al. "Power Efficient Memory Based Transistor-Memristor with CMOS Configuration Hybrid Mode Circuits for Future Neuromorphic Computation." Grenze International Journal of Engineering & Technology (GIJET), vol. 12, no. Part2, 2026, p. 4115.