APA (7th ed.) Citation

Papaphilippou, P. (2026). Highly Parallel Sorting Network Verification Using FPGAs. Chips, 5(1), 5. https://doi.org/10.3390/chips5010005

Chicago Style (17th ed.) Citation

Papaphilippou, Philippos. "Highly Parallel Sorting Network Verification Using FPGAs." Chips 5, no. 1 (2026): 5. https://doi.org/10.3390/chips5010005.

MLA (9th ed.) Citation

Papaphilippou, Philippos. "Highly Parallel Sorting Network Verification Using FPGAs." Chips, vol. 5, no. 1, 2026, p. 5, https://doi.org/10.3390/chips5010005.