View in EDS

Highly Parallel Sorting Network Verification Using FPGAs.

Saved in:

Bibliographic Details
Title:	Highly Parallel Sorting Network Verification Using FPGAs.
Authors:	Papaphilippou, Philippos¹
Source:	Chips; Mar2026, Vol. 5 Issue 1, p5, 12p
Database:	Applied Science & Technology Source

Description
ISSN:	26740729
DOI:	10.3390/chips5010005