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Implementation of Energy and EDP Efficient Adder Circuits at Sub Threshold Regime for Signal Processing Applications.

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Title: Implementation of Energy and EDP Efficient Adder Circuits at Sub Threshold Regime for Signal Processing Applications.
Authors: PAMULETI, CHALLA1, DAULA, S. M. SHAMSHEER2, GUNDALA, SRINIVASULU3, srinivasulugundala46@gmail.com, MADHURI, K.4, KUMAR, P. M. ASHOK5
Source: Journal of Active & Passive Electronic Devices; 2026, Vol. 20 Issue 2, p159-173, 15p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 193535833
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Implementation of Energy and EDP Efficient Adder Circuits at Sub Threshold Regime for Signal Processing Applications.
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Active+%26+Passive+Electronic+Devices%22">Journal of Active & Passive Electronic Devices</searchLink>; 2026, Vol. 20 Issue 2, p159-173, 15p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=193535833
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      – Code: eng
        Text: English
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        PageCount: 15
        StartPage: 159
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      – TitleFull: Implementation of Energy and EDP Efficient Adder Circuits at Sub Threshold Regime for Signal Processing Applications.
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            NameFull: DAULA, S. M. SHAMSHEER
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            NameFull: MADHURI, K.
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              Text: 2026
              Type: published
              Y: 2026
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