TRAN-THI, B. N., & LE, T. H. (2026). Reduced Check Node Storage for Hardware-Efficient LDPC Decoder. Radioengineering, 35(1), 56. https://doi.org/10.13164/re.2026.0056
Chicago Style (17th ed.) CitationTRAN-THI, Bich Ngoc, and Trong Hai LE. "Reduced Check Node Storage for Hardware-Efficient LDPC Decoder." Radioengineering 35, no. 1 (2026): 56. https://doi.org/10.13164/re.2026.0056.
MLA (9th ed.) CitationTRAN-THI, Bich Ngoc, and Trong Hai LE. "Reduced Check Node Storage for Hardware-Efficient LDPC Decoder." Radioengineering, vol. 35, no. 1, 2026, p. 56, https://doi.org/10.13164/re.2026.0056.
Warning: These citations may not always be 100% accurate.
