APA (7th ed.) Citation

N., P., & N., S. (2026). Low Power High Speed Finfet Dram Cell and 4x4 Array Design Using the Sleep Transistor Technique. Engineering, Technology & Applied Science Research, 16(2), 32955. https://doi.org/10.48084/etasr.15183

Chicago Style (17th ed.) Citation

N., Praveena, and Shylashree N. "Low Power High Speed Finfet Dram Cell and 4x4 Array Design Using the Sleep Transistor Technique." Engineering, Technology & Applied Science Research 16, no. 2 (2026): 32955. https://doi.org/10.48084/etasr.15183.

MLA (9th ed.) Citation

N., Praveena, and Shylashree N. "Low Power High Speed Finfet Dram Cell and 4x4 Array Design Using the Sleep Transistor Technique." Engineering, Technology & Applied Science Research, vol. 16, no. 2, 2026, p. 32955, https://doi.org/10.48084/etasr.15183.