Salcic, Z., Hui, D., Roop, P. S., & Biglari-Abhari, M. (2006). HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems. Microprocessors & Microsystems, 30(2), 72. https://doi.org/10.1016/j.micpro.2005.05.001
Chicago Style (17th ed.) CitationSalcic, Zoran, Dong Hui, Partha S. Roop, and Morteza Biglari-Abhari. "HiDRA—A Reactive Multiprocessor Architecture for Heterogeneous Embedded Systems." Microprocessors & Microsystems 30, no. 2 (2006): 72. https://doi.org/10.1016/j.micpro.2005.05.001.
MLA (9th ed.) CitationSalcic, Zoran, et al. "HiDRA—A Reactive Multiprocessor Architecture for Heterogeneous Embedded Systems." Microprocessors & Microsystems, vol. 30, no. 2, 2006, p. 72, https://doi.org/10.1016/j.micpro.2005.05.001.