An Area-Efficient High-Throughput Hybrid Interconnection Network for Single-Chip Parallel Processing.
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| Title: | An Area-Efficient High-Throughput Hybrid Interconnection Network for Single-Chip Parallel Processing. |
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| Authors: | Balkan, Aydin O.1, balkanay@umd.edu, Gang Qu1, gangqu@umd.edu, Vishkin, Uzi1, vishkin@umd.edu |
| Source: | DAC: Annual ACM/IEEE Design Automation Conference; 2008, p435-440, 6p, 4 Diagrams, 1 Chart, 3 Graphs |
| Database: | Applied Science & Technology Source |
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