An Asynchronous Ternary Logic Signaling System.
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| Title: | An Asynchronous Ternary Logic Signaling System. |
|---|---|
| Authors: | Felicijan, Tomaz, Furber, Steve B. |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems; December 2003, Vol. 11 Issue 6, p1114-1119, 6p |
| Database: | Applied Science & Technology Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 500926894 AccessLevel: 2 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=500926894 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2003.819571 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 6 StartPage: 1114 Titles: – TitleFull: An Asynchronous Ternary Logic Signaling System. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Felicijan, Tomaz – PersonEntity: Name: NameFull: Furber, Steve B. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: December 2003 Type: published Y: 2003 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 11 – Type: issue Value: 6 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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