APA (7th ed.) Citation

Kim, N. S., Flautner, K., & Blaauw, D. (2004). Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 167. https://doi.org/10.1109/TVLSI.2003.821550

Chicago Style (17th ed.) Citation

Kim, Nam Sung, Krisztian Flautner, and David Blaauw. "Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 2 (2004): 167. https://doi.org/10.1109/TVLSI.2003.821550.

MLA (9th ed.) Citation

Kim, Nam Sung, et al. "Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, 2004, p. 167, https://doi.org/10.1109/TVLSI.2003.821550.