APA (7th ed.) Citation

Antelo, E., Villalba, J., & Zapata, E. L. (2008). Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Transactions on Computers, 57(3), 404. https://doi.org/10.1109/TC.2007.70796

Chicago Style (17th ed.) Citation

Antelo, Elisardo, Julio Villalba, and Emilio L. Zapata. "Low-Latency Pipelined 2D and 3D CORDIC Processors." IEEE Transactions on Computers 57, no. 3 (2008): 404. https://doi.org/10.1109/TC.2007.70796.

MLA (9th ed.) Citation

Antelo, Elisardo, et al. "Low-Latency Pipelined 2D and 3D CORDIC Processors." IEEE Transactions on Computers, vol. 57, no. 3, 2008, p. 404, https://doi.org/10.1109/TC.2007.70796.